1. Field of the Invention
The invention relates generally to the field of microelectronic fabrication. More particularly, the invention relates to wafer processing system layouts.
2. Discussion of the Related Art
In the process of manufacturing a semiconductor device, such as an integrated circuit, numerous steps for micro-fabrication must be performed to form a finished device. One of these steps is the formation of a photoresist layer on a surface of a wafer. The step of forming the photo-resist layer is typically performed in a wafer processing apparatus that can be termed a track system. In the track system, a series of processes are performed on the surface of the wafer in a series of modules in order to form the photo-resist layer.
A conventional track system includes three sections. The first section, which is an interface section, is used to transfer wafers from cassettes to the track system and, conversely, from the track system back to cassettes. The second section of the track is called the process section. The process section includes a number of process modules such as resist coating spin modules, bake modules, chill modules and resist developing spin modules. The third section, which is another interface section, is used to transfer the wafers from the track system to a lithographic exposure tool and, conversely, from the exposure tool back to the track. The wafers are transported between these sections. The wafers are delivered to, processed by, removed from, and transported among the process modules by wafer transport mechanisms.
The time a wafer resides in a process module is called wafer total process time. The total process time consists of the actual process time, which is determined by the process recipe, plus the module overhead time which is a finction at least in-part of the electromechanical design of the module. Pre-process time is defined as the time that a wafer waits in a module before the actual process time starts. Similarly, post process time is defined as the time a wafer waits in a module to be removed after the completion of the actual process time. The time between removing a wafer from a module and delivering it to the next module is called wafer transport time.
Wafers are first fed from one or more wafer cassettes to the track system through the cassette end station. In the process of forming a photoresist film layer, the surface of the wafer is first treated and moisture is removed with heat and/or chemically. The wafer is then cooled and conveyed to a coating unit where a photo-resist polymer is evenly distributed on the surface of the wafer. The photo-resist coated wafer is then sent to a heating unit and the photo-resist polymer is converted into a stable film. At the completion of the heating step, the wafer is cooled and either conveyed to a cassette and stored as a treated wafer or, in most cases, transferred directly to the stepper, through a stepper interface. In the stepper, the stable film is exposed to a circuit pattern by a photolithographic technique. After exposure of the stable film, the wafer is transferred back to the track and is baked in a bake module to set the circuit pattern into the film The wafer is then cooled in a chill module and transferred to a spin develop module. In the spin develop module, a developing solution is applied onto the film to develop a portion of the film and then a rinse solution is applied to clean the surface of the wafer. Thereafter, the wafer is thermally treated in a bake module, cooled in a chill module and then returned to a cassette for storage and/or transport. The treating process and the sequence may vary depending upon the type of integrated circuit and the chemical compounds used in the processes. As a result, one or more of the sub-steps may be identified as a critical process which should be subject to minimum pre-process and/or post-process times. Further, a critical process should be subject to minimum variation of the pre-process and/or post-process times.
The maximum throughput of a track system is often limited by robot over utilization. Robot over utilization can be defined as a situation in which a lack of available robot resources causes an increase in post-process time. Conventionally, one or more of the following approaches has been utilized to address robot over utilization: (a) increasing robot speed; (b) adding more wafer handlers; and (c) providing robots with more than one dedicated wafer handling mechanism. Increasing robot speed increases the cost of the track system, reduces reliability and eventually reaches a design limit. Adding dedicated transfer arms to transport wafers among two adjacent and successive process modules constrains the system layout, increases the cost of the track system, and can not be used where modules are not adjacent and successive. Designing robots with more than one dedicated wafer handling mechanism adds to the complexity of the robot design, increases cost, and imposes additional restrictions on wafer handling.
Heretofore, the requirements of minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization referred to above have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.
A primary goal of the invention is to eliminate the need for dedicated transfer arms to avoid thermal cross-talk. Another primary goal of the invention is to minimize pre-process and/or post-process times. Another primary goal of the invention is to minimize variation of the pre-process and/or post-process times. Another primary goal of the invention is to reduce robot over utilization.
In accordance with these goals, there is a particular need for a wafer processing system layout where every wafer processing module in both a first process station and a second process station is accessible by (i) a respective process station robot and (ii) either a wafer cassette transfer robot or a stepper transfer robot. Also in accordance with these goals, there is a particular need for a wafer processing system layout where any wafer processing module in a wafer processing station can be accessed by at least two adjacent wafer transporters (e.g. robots). Also in accordance with these goals, there is a particular need for a wafer processing system layout where each of a first process station and a second process station are individually symmetrical with regard to wafer transporter access on both an X-axis and a Y-axis. Thus, it is rendered possible to simultaneously satisfy the above-discussed requirements of minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization, which, in the case of the prior art, are not simultaneously satisfied.
A first aspect of the invention is implemented in an embodiment that is based on a wafer processing apparatus, comprising: a first wafer transporter; a first process station coupled to said first wafer transporter, said first process station including: a first plurality of wafer processing stacks, each of said first plurality of wafer processing stacks including a first plurality of wafer processing modules, and a second wafer transporter coupled to said first plurality of wafer processing stacks, each of said first plurality of wafer processing modules adjacent, and accessible by, said second wafer transporter; a second process station coupled to said first wafer transporter, said second process station including: a second plurality of wafer processing stacks, each of said second plurality of wafer processing stacks including a second plurality of wafer processing modules, and a third wafer transporter coupled to said plurality of wafer processing stacks, each of said second plurality of wafer processing modules adjacent, and accessible by, said third wafer transporter; and a fourth wafer transporter coupled to both said first process station and said second process station, wherein each of said plurality of wafer processing modules in each of said plurality of wafer processing stacks is also accessible by either said first wafer transporter or said fourth wafer transporter. A second aspect of the invention is implemented in an embodiment that is based on a wafer processing apparatus, comprising: a first wafer transporter; a process station coupled to said first wafer transporter, said process station including: a plurality of wafer processing stacks, each of said plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to said plurality of wafer processing modules, each of said plurality of wafer processing modules adjacent, and accessible by, said second wafer transporter; and a third wafer transporter coupled to said process station, wherein any of said plurality of wafer processing modules in any of said plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters selected from the group consisting of said first wafer transporter, said second wafer transporter, and said third wafer transporter. A third aspect of the invention is implemented in an embodiment that is based on a wafer processing apparatus, comprising: a first wafer transporter; a first process station coupled to said first wafer transporter, said first process station including: a first plurality of wafer processing stacks, each of said first plurality of wafer processing stacks including a first plurality of wafer processing modules, and a second wafer transporter coupled to said first plurality of wafer processing stacks, each of said first plurality of wafer processing modules adjacent, and accessible by, said second wafer transporter; a second process station coupled to said first wafer transporter, said second process station including: a second plurality of wafer processing stacks, each of said second plurality of wafer processing stacks including a second plurality of wafer processing modules, and a third wafer transporter coupled to said plurality of wafer processing stacks, each of said second plurality of wafer processing modules adjacent, and accessible by, said third wafer transporter; and a fourth wafer transporter coupled to both said first process station and said second process station, wherein each of said first process station and said second process station are individually symmetrical with regard to wafer transporter access on both an X axis and a Y axis.
These, and other, goals and aspects of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such modifications.